Modified Differential Cascode Voltage Switch Logic Optimized for Sub-threshold Voltage Operation
MetadataShow full item record
Ultra-low sub-threshold voltage research has become increasingly important with the recent shift in consumer electronics towards low power designs for mobile, wearable, and implantable technologies. These applications are able to trade-off speed for reduced power consumption and reduced minimum operating voltage. This thesis studies circuit design solutions that focus on achieving the lowest minimum operating voltages. These applications are likely to be ones where the supply voltage may come from energy harvesting sources that are only able to source ultra-low voltages. The logic circuit presented in this thesis is a modified implementation of differential cascade voltage switch logic (DCVSL). Differential logic has improved ultra-low voltage performance over static CMOS logic and the modification to DCVSL offers a logic structure that can implement multi-input AND/NAND and OR/NOR gates while maintaining a stack height of one. This logic circuit is referred in this thesis as MOD-DCVSL. The modification requires the use of capacitive boosting to allow for normal logic operation. The results of this thesis show that differential logic styles are able to perform at lower minimum operating voltages compared to static CMOS logic styles but at the cost of larger delay and power compared to static CMOS. On average the differential implementations could operate at a minimum supply voltage 5mV lower than CMOS for two input implementations and 10mV lower for three input implementations. The delay of differential implementations was approximately double for both two and three input implementations. The power of the differential implementations are approximately 20% higher than static CMOS for two input implementations but this gap is narrowed to approximately 10% for three input implementations, here the lower minimum operating voltages allowed for decreased power consumption. Due to the consistently lower delay, static CMOS had a lower power delay product than the differential logic. When comparing only the differential logic, MOD-DCVSL offered negligible difference for two input implementations but was able to improve delay by 7% and power by 11% in the three input implementations.