Performance Limit and Design Strategy of Black Phosphorus Field-Effect Transistors
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Recently, a novel two-dimensional (2D) semiconductor of few-layer black phosphorus (BP) or phosphorene has been explored extensively for future electronic device applications. BP field-effect transistors (FETs) exhibited promising device characteristics such as high field-effect mobility (μ_eff > 1,000 cm²/V-s), large on current (Ion ~300 μA/μm), and large on-off current ratio (Ion/Ioff > 10⁸). In principle, the performance of BP FETs can be further improved by scaling the device, but their performance limit has not been explored particularly for multilayer BP FETs. In addition, most BP devices were studied individually without performing optimization in material or device parameters, and therefore, comprehensive design strategies for different target applications are currently absent. In this thesis, performance limit and design strategy of phosphorene FETs will be discussed by means of self-consistent atomistic quantum transport simulations using non-equilibrium Green’s function (NEGF) formalism. First, the scaling limit of bilayer BP FET is investigated. It is shown that, while the scaling of gate dielectric monotonically enhances the overall performance of bilayer BP FETs, channel length can only be scaled down to ~8 nm due to significant short-channel effects. Bilayer phosphorene FETs are benchmarked against bilayer MoS₂ and WSe₂ FETs along with a monolayer phosphorene device, which reveals that bilayer phosphorene FETs have favorable switching characteristics over other similar 2D bilayer semiconductor devices, making both monolayer and bilayer phosphorene attractive for future switching applications. In general, thickness or the number of layers in 2D semiconductors is a key parameter to determine the material’s electronic properties and the overall device performance of 2D material electronics. Therefore, the impact of having different number of phosphorene layers on the transistor performance is investigated next, considering two specific target applications of high-performance and low-power devices. Our results suggest that, for high-performance applications, monolayer phosphorene should be utilized in conventional FET structure since it can provide the equally large on current as other multilayer phosphorenes (Ion > 1 mA/μm) without showing a penalty of relatively lower density of states, along with favorableness for steep switching and large immunity to gate-induced drain leakage. On the other hand, more comprehensive approach is required for investigating low-power devices, where operating voltage, doping concentration, and channel length should be carefully engineered along with the thickness of phosphorene in the tunnel FET (TFET) structure to achieve ultra-low leakage current without sacrificing on current significantly. Our extensive simulation results revealed that either bilayer or trilayer phosphorene can provide the best performance in TFETs with the maximum Ion/Ioff of ~2×10¹¹ and the subthreshold swing as low as 13 mV/dec. In addition, our comparative study of phosphorene-based conventional FET and TFET clearly shows the feasibility and the limitation of each device for different target applications, providing irreplaceable insights into the design strategy of phosphorene FETs that can be also extended to other similar layered material electronic devices.