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dc.contributor.authorLaor, Ariel 19:46:30 (GMT) 04:50:07 (GMT)
dc.description.abstractFlip chip is an electronic packaging technology that is becoming more popular in first level electronic packaging as the need for high density electrical interconnects becomes more relevant. The parallel nature of flip chip and harsh thermomechanical treatment introduces stress to the microchip and substrate. This is primarily caused by the application of high forces and mismatch in the thermal coefficient of expansion among the materials in the system. Other noise factors like misalignment, parallelism mismatch, warpage, pillar height variation, and temperature variation can weaken the bonding process. Unlike wire bonding, there is a lack of tools available for quality assessment of the flip chip process in-situ locally at the interconnect sites. There are however some existing wire bonding sensor tools which can be modified to be useful for optimization of flip chip equipment and processes. A 4x3 mm CMOS chip is designed to record XYZ force and temperature profiles in-situ on a 2-dimensional surface during a simulated flip chip process. This was done as a low risk proof of concept to evaluate if the wire bonding tools can be adapted for a flip chip application. 95 μm square Al bond pads arranged in a square 8x8 array with 400 μm pitch have embedded piezoresistive force sensors and local top metal resistive temperature detectors. The chip is packaged with auxiliary wire bonds to deliver power and capture signals while operating under a bond head. Ball bumps 73 μm in diameter are deposited onto the sensor pads using 4N Au wire. Z sensors are calibrated using a modified automatic wire bonder. A normalized sensitivity of SN=1.39 mV/V/N is measured. Temperature sensors are calibrated at 50 °C using Kelvin probing yielding 186.94 Ω. A 3x3 mm Si wafer with Al patterning is used as a dummy pressure plate for touchdowns on the sensor chip with an experimental setup advanced process bond head. Force and temperature signals are recorded locally at each bump. 80 N force with 200 °C temperature ramps ups are applied. Evidence of tilt and thermal expansion are detected. The prototype is demonstrated successfully and identified the most stressful stage of the bonding which occurred during thermal transients, i.e. during the short lived overshoot period of maximum stress in the force signals observed immediately after the application of heat to the system.en
dc.publisherUniversity of Waterlooen
dc.subjectFlip Chip Electronic Packaging CMOSen
dc.titleA Novel 8x8 CMOS Sensor Array for Thermal Compression Bonding with in-situ XYZ Force and Temperature Measurementen
dc.typeMaster Thesisen
dc.pendingfalse and Mechatronics Engineeringen Engineeringen of Waterlooen
uws-etd.degreeMaster of Applied Scienceen
uws-etd.embargo.terms1 yearen
uws.contributor.advisorMichael, Mayer
uws.contributor.affiliation1Faculty of Applied Health Sciencesen

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