Browsing University of Waterloo by Subject "SRAM"
Now showing items 1-11 of 11
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Circuit Design of SRAM Physically Unclonable Functions
(University of Waterloo, 2017-09-06)A Physically Unclonable Function (PUF) is an entity that reliably provides a unique response to a given challenge and cannot be easily duplicated physically. PUFs are an alternative to using non-volatile memory (NVM) for ... -
A Comparative Analysis of 6T and 10T SRAM Cells for Sub-threshold Operation in 65 nm CMOS Technology
(University of Waterloo, 2016-09-27)The aggressive approach of the integrated electronics industry towards scaling and the growing trend of low-power applications have led to major research interest in ultra-low power integrated circuits. One of the integrated ... -
Design and Analysis of an Adjacent Multi-bit Error Correcting Code for Nanoscale SRAMs
(University of Waterloo, 2014-12-02)Increasing static random access memory (SRAM) bitcell density is a major driving force for semiconductor technology scaling. The industry standard 2x reduction in SRAM bitcell area per technology node has lead to a ... -
Design of Variation-Tolerant Circuits for Nanometer CMOS Technology: Circuits and Architecture Co-Design
(University of Waterloo, 2008-11-28)Aggressive scaling of CMOS technology in sub-90nm nodes has created huge challenges. Variations due to fundamental physical limits, such as random dopants fluctuation (RDF) and line edge roughness (LER) are increasing ... -
Digital Timing Control in SRAMs for Yield Enhancement and Graceful Aging Degradation
(University of Waterloo, 2010-08-16)Embedded SRAMs can occupy the majority of the chip area in SOCs. The increase in process variation and aging degradation due to technology scaling can severely compromise the integrity of SRAM memory cells, hence resulting ... -
Low-Power, Low-Voltage SRAM Circuits Design For Nanometric CMOS Technologies
(University of Waterloo, 2011-08-30)Embedded SRAM memory is a vital component in modern SoCs. More than 80% of the System-on-Chip (SoC) die area is often occupied by SRAM arrays. As such, system reliability and yield is largely governed by the SRAM's performance ... -
Robust Design of Variation-Sensitive Digital Circuits
(University of Waterloo, 2011-07-11)The nano-age has already begun, where typical feature dimensions are smaller than 100nm. The operating frequency is expected to increase up to 12 GHz, and a single chip will contain over 12 billion transistors in 2020, ... -
Statistical Yield Analysis and Design for Nanometer VLSI
(University of Waterloo, 2010-08-20)Process variability is the pivotal factor impacting the design of high yield integrated circuits and systems in deep sub-micron CMOS technologies. The electrical and physical properties of transistors and interconnects, ... -
Struck-at Fault Tolerance with Emerging Technology RAM in the NeuroSim MLP Neural Network System
(University of Waterloo, 2021-09-15)After decades of technology advancements, benefits from conventional dimensional scaling and effective scaling such as strain and high-k gate dielectrics are diminishing. In the post-Moore era, interests gathers around ... -
Subthreshold SRAM Design for Energy Efficient Applications in Nanometric CMOS Technologies
(University of Waterloo, 2018-01-23)Embedded SRAM circuits are vital components in a modern system on chip (SOC) that can occupy up to 90% of the total area. Therefore, SRAM circuits heavily affect SOC performance, reliability, and yield. In addition, most ... -
Variability-Aware Design of Static Random Access Memory Bit-Cell
(University of Waterloo, 2008-07-03)The increasing integration of functional blocks in today's integrated circuit designs necessitates a large embedded memory for data manipulation and storage. The most often used embedded memory is the Static Random Access ...