A Comparative Analysis of 6T and 10T SRAM Cells for Sub-threshold Operation in 65 nm CMOS Technology

Abstract

The aggressive approach of the integrated electronics industry towards scaling and the growing trend of low-power applications have led to major research interest in ultra-low power integrated circuits. One of the integrated circuit areas most affected by this revolution is computer memory. In this thesis, a 10-Transistor Static Random Access Memory is compared to a 6-Transistor Static Random Access Memory in the subthreshold region of operation for a 65nm technology node. This comparison focuses primarily on the stability of memory cells in performing read and write operations. The use of 3-dimentional graphs in this thesis is to better compare differences and to give a feedback to memory designers about the design possibilities. A low-power Write Margin improvement method is proposed for the 10-Transistor cell to bring its stability to a standard comparable to that of its 6-transistor counterpart.