WCET Preserving Memory Management for High Performance Mixed Criticality Systems

Abstract

This thesis explores innovative memory and cache management mechanisms for mixed-criticality systems that aim to improve the performance of the system while maintaining its predictability. We consider mixed-criticality systems where requestors may issue latency-critical (LTC) and non-latency-critical (NLTC) requests. LTC requests must adhere to strict latency bounds imposed by safety-critical applications, but timely servicing NLTC requests is necessary to maximize overall system performance in the average case. In this thesis, we focus on addressing the challenges of processing LTC and NLTC memory requests in mixed-criticality systems and the limitations of existing cache management mechanisms designed to improve the system's average performance. Accordingly, we introduce two key contributions: one at the memory arbitration level and the other at the cache controller level.

In the first contribution, we propose DAMA, a dual arbitration mechanism that imposes an upper bound on the cumulative latency of LTC requests without unduly impacting the performance of NLTC requests. DAMA comprises a high-performance arbiter, a real-time arbiter, and a mechanism that constantly monitors the cumulative latency of requests suffered by each requestor. DAMA primarily executes in high-performance mode and only switches to real-time mode in the rare instances when its incorporated mechanism detects a violation of a task's timing guarantee. We demonstrate the effectiveness of our arbitration scheme by adapting a predictable prefetcher that issues NLTC requests and attaching it to the L1 caches of our cores. We show both formally and experimentally that DAMA provides timing guarantees for LTC requests while processing other NLTC requests. Our evaluation demonstrates that with a negligible overhead of less than 1% on the cumulative latency bound of LTC requests, DAMA can achieve an equivalent average performance to a prefetcher that processes requests under a high-performance arbitration scheme.

In the second contribution, we introduce a novel hardware mechanism at the cache controller level that leverages the LRU age bits to perform duration-based cache locking. Our proposed mechanism dynamically locks and unlocks cache lines for different durations at run-time, without the need to modify the program's code. We further devise a heuristic that analyzes a program's loop structure and selects the set of addresses to be locked in a L1 instruction cache alongside their locking durations. Evaluation results show that our duration-based locking mechanism significantly reduces initialization overhead and eliminates the need for program code modifications. The proposed mechanism achieves a performance comparable to the dynamic approach, which adjusts locked program content at runtime.