CMOS Front-End Circuits in 45-nm SOI Suitable for Modular Phased-Array 60-GHz Radios

dc.contributor.advisorLong, John
dc.contributor.authorEltaliawy, Ayman
dc.date.accessioned2021-01-26T15:27:02Z
dc.date.available2021-01-26T15:27:02Z
dc.date.issued2021-01-26
dc.date.submitted2021-01-15
dc.description.abstractNext Fifth-generation (5G) wireless technologies enabling ultra-wideband spectrum availability and increased system capacity can achieve multi-gigabit/s (Gbps) data rates suitable for ultra-high-speed internet access around the 60-GHz band (i.e., Wi-Gig Technology). This mm-wave band is unlicensed and experiences high propagation power losses. Therefore, it is suitable for short-range communications and requires antenna arrays to satisfy the link budget requirements. Half-duplex reconfigurable phased-array transceivers require wideband, low-cost, highly integrated front-end circuits such as bilateral RF switches, low-noise/power amplifiers, passive RF splitters/combiners, and phase shifters implemented in deep sub-micron CMOS. In this dissertation, analysis, design, and verification of essential CMOS front-end components are covered and fabricated in GlobalFoundries 45-nm RF-SOI CMOS technology. Firstly, a fully-differential, single-pole, single-throw (SPST) switch capable of high isolation in broadband CMOS transceivers is described. The SPST switch realizes better than 50-dB isolation (ISO) across DC to 43 GHz while maintaining an insertion loss (IL) below 3 dB. Measured RF input power for 1-dB compression (IP1dB) of the IL is +19.6 dBm, and the measured input third-order intercept point (IIP3) is +30.4 dBm (both assuming differential inputs at 20 GHz). The prototype has an active area of 0.0058 mm^2. Secondly, a single-pole double-throw (SPDT) switch is implemented using the SPST concept by using a balun to convert the shared differential path to a single-ended antenna port. The SPDT simulations predict less than 3.5-dB IL and greater than 40-dB ISO across 55 to 65 GHz frequency band. An IP1dB of +21 dBm is expected from large-signal simulations. The prototype has an active area of 0.117 mm^2. Thirdly, a fully-differential switched-LC topology adopted with slow-wave artificial transmission line concept, and phase inversion network is described for a 360-degree phase shift range with 11.25-degree phase resolution. The average IL of the complete phase shifter is 5.3 dB with less than 1-dB rms IL error. Furthermore, the IP1dB of the phase shifter is +16 dBm. The prototype has an active area of 0.245 mm^2. Lastly, a fully-differential, 2-stage, common-source (CS) low-noise amplifier (LNA) is developed with wideband matching from 57.8 GHz to 67 GHz, a maximum simulated forward power gain of 20.8 dB, and a minimum noise figure of 3.07 dB. The LNA consumes 21 mW and predicts an OP1dB of 4.8 dBm from the 1-V supply. The LNA consumes an active area of 0.028 mm^2.en
dc.identifier.urihttp://hdl.handle.net/10012/16734
dc.language.isoenen
dc.pendingfalse
dc.publisherUniversity of Waterlooen
dc.subjectmm-Wave SPDT switchen
dc.subject60-GHz banden
dc.subjecthigh-isolation RF switchen
dc.subjectlow-loss phase shifteren
dc.subjectCMOS phased-array transceiveren
dc.subjectRF-SOI CMOSen
dc.subjectfully-differential CMOS transceiveren
dc.subjectRF/mm-Wave low-noise amplifieren
dc.subjectpassive phase shifteren
dc.titleCMOS Front-End Circuits in 45-nm SOI Suitable for Modular Phased-Array 60-GHz Radiosen
dc.typeDoctoral Thesisen
uws-etd.degreeDoctor of Philosophyen
uws-etd.degree.departmentElectrical and Computer Engineeringen
uws-etd.degree.disciplineElectrical and Computer Engineeringen
uws-etd.degree.grantorUniversity of Waterlooen
uws-etd.embargo.terms0en
uws.contributor.advisorLong, John
uws.contributor.affiliation1Faculty of Engineeringen
uws.peerReviewStatusUnrevieweden
uws.published.cityWaterlooen
uws.published.countryCanadaen
uws.published.provinceOntarioen
uws.scholarLevelGraduateen
uws.typeOfResourceTexten

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