Low-power and Radiation Hardened TSPC Registers

Abstract

Battery-operated systems require power and energy-efficient circuits to extend their battery life. Flip-flops (FFs) are a basic component of digital circuits, and their power consumption and speed significantly impact the overall performance of a digital system. A clock network in a complex System-on-Chip (SoC) consumes a substantial amount of power. Additionally, often pipelines are used to enhance the system throughput, which puts additional burden on the clock network. Arguably, a flip-flop with fewer clock transistors will reduce its power burden on the clock network. This research proposes three very low-power Single-edge Triggered (SET) True Single-phase Clock (TSPC) FFs with only two and three clock transistors. Moreover, a scan-chain of 256 FFs and AES-128 encryption engine were designed as a benchmark to further investigate the power savings of the proposed FFs. Additionally, we have also designed three very low-power Dual-edge Triggered (DET) latch-multiplexer type TSPC FFs with only eight and ten clock transistors to sample the data at both positive and negative clock edges.

Furthermore, high-performance computations in Integrated Circuits (ICs) are increasingly needed for space and safety-critical applications. ICs are subjected to high-energy ionizing particles in the radiant space environment, which will cause the device performance to degrade or even fail. A Single Event Upset (SEU) occurs in the logic circuit when an ion strikes a device’s sensitive node, changing the output from 0 to 1 or from 1 to 0. In radiant applications, ICs contain storage cells like FFs, latches, or Static Random Access Memories (SRAM), and always experience SEU. Although package and process engineering can minimize alpha particles, cosmic neutrons cannot be physically blocked. Therefore, for high reliability systems, soft error tolerant circuit designs are crucial. Traditional Radiation Hardened By Design (RHBD) techniques have some trade-offs between area, speed, power, and energy consumption. Thus, new designs are required to reduce these penalties. This research proposes two high-performance, low-power, low-energy, and low-area RHBD TSPC FFs with only four and five clock transistors suitable for space and safety-critical applications.