Cryogenic CMOS Compact Modeling for Cryo-Electronic Applications
| dc.contributor.author | Elgabra, Hazem | |
| dc.date.accessioned | 2023-09-27T19:41:01Z | |
| dc.date.issued | 2023-09-27 | |
| dc.date.submitted | 2023-09-22 | |
| dc.description.abstract | Quantum computing holds the promise of a monumental leap in computational power, enabling the resolution of previously insurmountable problems with astonishing speed compared to classical computers. Emerging computing paradigms, including Shor's factoring algorithm, Grover's searching algorithm, quantum simulations, protein folding, and more, stand on the brink of feasibility, thanks to quantum computers. However, despite impressive recent advancements in quantum computing, demonstrated systems featuring anywhere between a few to around a hundred physical qubits remain significantly distant from achieving quantum supremacy over classical computing, which demands the utilization of millions of physical qubits. This formidable challenge is known as the scaling problem. Implementing large-scale quantum computing systems is faced with numerous hurdles, particularly where each qubit necessitates precise control under extremely low cryogenic temperatures (<1 K). Complementary metal-oxide-semiconductor (CMOS) technology, the cornerstone of classical computer scaling, emerges as a promising solution for scaling quantum computers. CMOS technology offers deep miniaturization and versatility, functioning seamlessly at both room temperature (RT) and cryogenic temperatures (cryoT). CMOS is compatible with the spin qubits in semiconductor quantum dots (one of the various methods of implementing qubits that exhibit long coherence time) offering integration compatibility especially from the fabrication perspective. It is this kind of tight integration that may ultimately hold the key to resolving the quantum scaling problem, bridging the gap between the current state of quantum computing and its promising potential. Nevertheless, current circuit design environments lack support for operating temperatures near cryoT. This lack of support is centered in the often overlooked component known as the compact model. Compact models act as the blueprint that informs circuit simulators of how circuit elements behave under various operating conditions. This component is composed of simplified mathematical formulas that bridge the gap between the element's physical model and simulation engines. In order to obtain accurate simulation results necessary for cryo-circuits design the compact model must be accurate. To obtain precise simulation results necessary for cryo-circuit design, it is imperative to understand and incorporate the effects of cryoT on metal-oxide-semiconductor field-effect-transistors (MOSFETs) into the compact model. This thesis is one of the first attempts to develop cryogenic MOSFET compact model based on virtual source concept, through theoretical investigation and experimental validation. The cold temperature effects on MOSFETs are studied and integrated into the existing MIT virtual-source model (MVS), expanding its temperature range to include deep cryoT in the range of few Kelvin. To achieve this, sample devices from multiple commercial technology nodes are characterized in RT down to deep cryoT. The thesis outlines the measurement setup and explores a range of predicted and unexpected cryogenic phenomena within the transistor. Good agreement between experimental data and modeled data is obtained between 300 K and 4 K for 20, 28, and 65 nm bulk CMOS technology nodes. However, merely developing a cryogenic compact model is insufficient for its adoption and practical deployment. Extraction and fitting tools are therefore developed alongside the model. To support circuit design on industrial tools and validate the model, the compact model is implemented Verilog-A. Subsequently, a cryogenic circuit simulation is demonstrated using industry-standard electronic design automation (EDA) tools. This demonstration underscores the viability of the model to facilitate cryo-circuit design for quantum computing, representing a significant step towards realizing the potential of quantum computing in practical applications. | en |
| dc.identifier.uri | http://hdl.handle.net/10012/19966 | |
| dc.language.iso | en | en |
| dc.pending | false | |
| dc.publisher | University of Waterloo | en |
| dc.subject | compact modeling | en |
| dc.subject | CMOS | en |
| dc.subject | cryogenic | en |
| dc.subject | MOSFET | en |
| dc.subject | cryo-CMOS | en |
| dc.subject | virtual source | en |
| dc.subject | MVS | en |
| dc.subject | cryoMVS | en |
| dc.title | Cryogenic CMOS Compact Modeling for Cryo-Electronic Applications | en |
| dc.type | Doctoral Thesis | en |
| uws-etd.degree | Doctor of Philosophy | en |
| uws-etd.degree.department | Electrical and Computer Engineering | en |
| uws-etd.degree.discipline | Electrical and Computer Engineering | en |
| uws-etd.degree.grantor | University of Waterloo | en |
| uws-etd.embargo | 2025-09-26T19:41:01Z | |
| uws-etd.embargo.terms | 2 years | en |
| uws.contributor.advisor | Wei, Lan | |
| uws.contributor.affiliation1 | Faculty of Engineering | en |
| uws.peerReviewStatus | Unreviewed | en |
| uws.published.city | Waterloo | en |
| uws.published.country | Canada | en |
| uws.published.province | Ontario | en |
| uws.scholarLevel | Graduate | en |
| uws.typeOfResource | Text | en |
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