Browsing Waterloo Research by Subject "Latency Analysis"
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Worst Case Latency Analysis for Hoplite FPGA-based NoC
(2017-10-30)Overlay NoCs, such as Hoplite, are cheap to implement on an FPGA but provide no bounds on worst-case routing latency of packets traversing the NoC due to deflection routing. In this paper, we show how to adapt Hoplite to ...