Now showing items 1-2 of 2

    • A Composable Worst Case Latency Analysis for Multi-Rank DRAM Devices under Open Row Policy 

      Wu, Zheng Pei; Pellizzoni, Rodolfo; Guo, Danlu (Springer, 2017-04-12)
      As multi-core systems are becoming more popular in real-time embedded systems, strict timing requirements for accessing shared resources must be met. In particular, a detailed latency analysis for Double Data Rate Dynamic ...
    • DuoMC: Tight DRAM Latency Bounds with Shared Banks and Near-COTS Performance 

      Mirosanlou, Reza; Hassan, Mohamed; Pellizzoni, Rodolfo (ACM International Symposium on Memory Systems (MEMSYS 2021), 2021-09-27)
      DRAM memory controllers (MCs) in COTS systems are designed primarily for average performance, offering no worst-case guarantees, while real-time MCs provide timing guarantees at the cost of a significant average performance ...


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