Browsing Electrical and Computer Engineering by Subject "temporal logic"
Now showing items 1-2 of 2
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Extracting Counterexamples from Transitive-Closure-Based Model Checking
(IEEE, 2019)We address the problem of how to extract counterexamples for the transitive-closure-based model checking (TCMC) technique. TCMC is a representation of the CTLFC (CTL with fairness constraints) model checking problem in ... -
RuSTL: Runtime Verification using Signal Temporal Logic
(University of Waterloo, 2019-04-23)A system is classified to be a safety-critical system if its failure and/or malfunction of these devices may result in severe injuries or in extreme cases loss of human life. Such systems are all around us, examples of ...