Browsing Electrical and Computer Engineering by Subject "Timing analysis"
Now showing items 1-2 of 2
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A Composable Worst Case Latency Analysis for Multi-Rank DRAM Devices under Open Row Policy
(Springer, 2017-04-12)As multi-core systems are becoming more popular in real-time embedded systems, strict timing requirements for accessing shared resources must be met. In particular, a detailed latency analysis for Double Data Rate Dynamic ... -
Predictable Shared Memory Resources for Multi-Core Real-Time Systems
(University of Waterloo, 2017-04-18)A major challenge in multi-core real-time systems is the interference problem on the shared hardware components amongst cores. Examples of these shared components include buses, on-chip caches, and off-chip dynamic random ...