Now showing items 1-4 of 4

    • HopliteBuf FPGA Network-on-Chip: Architecture and Analysis 

      Garg, Tushar (University of Waterloo, 2019-04-22)
      We can prove occupancy bounds of stall-free FIFOs used in deflection-free, low-cost, and high-speed FPGA overlay Network-on-chips (NoCs). In our work, we build on top of the HopliteRT livelock-free overlay NoC with an ...
    • Managing HBM’s bandwidth in Multi-Die FPGAs using Overlay NoCs 

      Kuttuva Prakash, Srinirdheeshwar (University of Waterloo, 2022-01-18)
      We can improve HBM bandwidth distribution and utilization on a multi-die FPGA like Xilinx Alveo U280 by using Overlay Network-on-Chips (NoCs). HBM in Xilinx Alveo U280 offers 8GBs of memory capacity with a theoretical ...
    • NengoFPGA: an FPGA Backend for the Nengo Neural Simulator 

      Morcos, Benjamin (University of Waterloo, 2019-08-22)
      Low-power, high-speed neural networks are critical for providing deployable embedded AI applications at the edge. We describe a Xilinx FPGA implementation of Neural Engineering Framework (NEF) networks with online learning ...
    • Worst-Case Latency Analysis for the Versal Network-on-Chip 

      Elmor Lang, Ian (University of Waterloo, 2022-01-18)
      The recent line of Versal FPGA devices from Xilinx Inc. includes a hard Network-On-Chip (NoC) embedded in the programmable logic, designed to be a high-performance system-level interconnect. While the target markets for ...

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