| dc.description.abstract | Analog integrated circuit design has become increasingly difficult in modern fabrication processes. The motivation for digital speed has posed problems for mixed-signal projects that wish to implement digital and analog blocks on the same chip. With the introduction of multigate transistors (also known as FinFETs), the challenges for analog design increase. This is due to the fact that FinFET devices will no longer have a continuum of width and lengths sizes (as previous technologies have exhibited), but instead, these parameters are now quantized. This work proposes a potential solution to the fixed-length problem, in a topology termed the ``series-stack".
Foundries plan to launch the FinFET technology with a number of fixed-sized transistors (typically with minimum length). To the digital designer, this poses little problem, but for analog circuits, not being able to control device length compromises the ability to meet gain specifications. This work explores a simple method for implementing longer devices: connecting transistors in series, herein called series-stack. To test the feasibility of this architecture, a two-stage CMOS operational amplifier is designed. In lieu of application-specific design constraints, a structure strategy is presented. A key motivation for the series-stack as well as the design strategy is to bring the analog design process up a level of abstraction. The amplifier was planned to be put through the entire design cycle, from conception to lab testing, giving insight into the accuracy of simulation models.
Schematic and post-layout results were collected from the TSMC 65nm kit. Analysis of the results yield obvious simulation discrepancies. Namely, the schematic simulation vastly overestimates the parasitic resistances and capacitances when using finger-gate techniques. This is an important problem for which possible solutions are discussed. Additionally, the results show significant differences between conventional bulk length and series-stack, with a relative error spanning from 2% to 20% depending on the performance metric. Yet, most discrepancies are expected, and the two implementations follow similar trends with respect to current density and length.
A final verdict cannot be delivered until physical chip testing is conducted, which is left to future work (complications in timeline did not allow for the lab test results to be included). Although chip testing was not completed, a thorough testing plan is formulated. Despite physical testing, the series-stack is deemed a suitable alternative to long transistor designs, especially when considering the organizational advantages at the layout level. | en |
