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dc.contributor.authorSaffih, Fayçalen
dc.date.accessioned2006-08-22 13:53:20 (GMT)
dc.date.available2006-08-22 13:53:20 (GMT)
dc.date.issued2005en
dc.date.submitted2005en
dc.identifier.urihttp://hdl.handle.net/10012/820
dc.description.abstractElectronic imaging technologies are faced with the challenge of power consumption when transmitting large amounts of image data from the acquisition imager to the display or processing devices. This is especially a concern for portable applications, and becomes more prominent in increasingly high-resolution, high-frame rate imagers. Therefore, new sampling techniques are needed to minimize transmitted data, while maximizing the conveyed image information. <br /><br /> From this point of view, two approaches have been proposed and implemented in this thesis: <ol> <li> A system-level approach, in which the classical 1D row sampling CMOS imager is modified to a 2D ring sampling pyramidal architecture, using the same standard three transistor (3T) active pixel sensor (APS). </li> <li> A device-level approach, in which the classical orthogonal architecture has been preserved while altering the APS device structure, to design an expandable multiresolution image sensor. </li> </ol> A new scanning scheme has been suggested for the pyramidal image sensor, resulting in an intrascene foveated dynamic range (FDR) similar in profile to that of the human eye. In this scheme, the inner rings of the imager have a higher dynamic range than the outer rings. The pyramidal imager transmits the sampled image through 8 parallel output channels, allowing higher frame rates. The human eye is known to have less sensitivity to oblique contrast. Using this fact on the typical oblique distribution of fixed pattern noise, we demonstrate lower perception of this noise than the orthogonal FPN distribution of classical CMOS imagers. <br /><br /> The multiresolution image sensor principle is based on averaging regions of low interest from frame-sampled image kernels. One pixel is read from each kernel while keeping pixels in the region of interest at their high resolution. This significantly reduces the transferred data and increases the frame rate. Such architecture allows for programmability and expandability of multiresolution imaging applications.en
dc.formatapplication/pdfen
dc.format.extent7973840 bytes
dc.format.mimetypeapplication/pdf
dc.language.isoenen
dc.publisherUniversity of Waterlooen
dc.rightsCopyright: 2005, Saffih, Fayçal. All rights reserved.en
dc.subjectElectrical & Computer Engineeringen
dc.subjectCMOS image sensoren
dc.subjectPyramidal image sensoren
dc.subjectMultiresolution image sensoren
dc.subject2D samplingen
dc.subjectFoveated Dynamic Range (FDR)en
dc.subjectVideophoneen
dc.subjectVideo communicationen
dc.subjectRemote imagingen
dc.titleFoveated Sampling Architectures for CMOS Image Sensorsen
dc.typeDoctoral Thesisen
dc.pendingfalseen
uws-etd.degree.departmentElectrical and Computer Engineeringen
uws-etd.degreeDoctor of Philosophyen
uws.typeOfResourceTexten
uws.peerReviewStatusUnrevieweden
uws.scholarLevelGraduateen


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