Noise Analysis and Measurement of Integrator-based Sensor Interface Circuits for Fluorescence Detection in Lab-on-a-chip Applications

Abstract

Lab-on-a-chip (LOC) biological assays have the potential to fundamentally reform healthcare. The move away from centralized facilities to Point-of-Care (POC) testing of biological assays would improve the speed and accuracy of these, thereby improving patient care. Before LOC can be realized, a number of challenges must be addressed: the need for expert users must be abstracted away; the manufacturing cost of $5 per test threshold must be met; and the supporting infrastructure must be integrated down to an easily portable size. These challenges can be addressed with the deposition of microfluidics on CMOS chips. By designing application specific integrated circuits (ASICs) much of the automation and the supporting infrastructure needed to run these assays can be integrated into the chip. Additionally, CMOS fabrication is some of the most optimized manufacturing in industry today.

One of the central challenges with LOC on ASIC is the signal acquisition from the microfluidics into the CMOS. Optical sensing of fluorescence is one form of sensing used for LOC assays. Despite a large literature, there has not been a strong demonstration of monolithic LOC fluorescence detection (FD) for low concentration samples. This work explores the limit-of-detection (LOD) for LOC FD through analysis of the signal and noise of a proposed acquisition channel.

The proposed signal acquisition channel consists of an on chip photodiode and integrator based amplification circuits. A hand analysis of the signal propagation through the channel and the noise sources introduced by the circuitry, is performed. This analysis is used to establish relationships between different circuit parameters and the LOD of a hypothetical LOC device. The hand analysis is verified through simulation and the acquisition channel is implemented in: (i) the Austrian Microsystems 350nm CMOS process, (ii) discrete components. Testing of the CMOS chip revealed several issues not identified in extracted simulation; however, the discrete integrator demonstrated many of the trends predicted by the hand analysis and simulations and achieved a LOD of 7.2$\mu M$. This analysis provides insight into the engineering trade-offs required to improve the LOD, to enable more wide spread application of LOC FD.