|dc.description.abstract||Flash Analog-to-Digital Converters (ADCs), targeting optical
communication standards, have been reported in SiGe BiCMOS
technology. CMOS implementation of such designs faces two
challenges. The first is to achieve a high sampling speed, given the
lower gain-bandwidth (lower ft) of CMOS technology. The second
challenge is to handle the wide bandwidth of the input signal with a
certain accuracy. Although the first problem can be relaxed by using
the time-interleaved architecture, the second problem remains as a
main obstacle to CMOS implementation. As a result, the feasibility
of the CMOS implementation of ADCs for such applications, or other
wide band applications, depends primarily on achieving a very small
input capacitance (large bandwidth) at the
In the flash architecture, the input capacitance is traded off for
the achievable accuracy. This tradeoff becomes tighter with
technology scaling. An effective way to ease this tradeoff is to use
resistive offset averaging. This permits the use of smaller area
transistors, leading to a reduction in the ADC input capacitance. In
addition, interpolation can be used to decrease the input
capacitance of flash ADCs. In an interpolating architecture, the
number of ADC input preamplifiers is reduced significantly, and a
resistor network interpolates
the missing zero-crossings needed for an N-bit conversion. The resistive network also averages
out the preamplifiers offsets. Consequently, an interpolating network works also as an averaging network.
The resistor network used for averaging or interpolation causes a
systematic non-linearity at the ADC transfer characteristics edges.
The common solution to this problem is to extend the preamplifiers
array beyond the input signal voltage range by using dummy
preamplifiers. However, this demands a corresponding extension of
the flash ADC reference-voltage resistor ladder. Since the voltage
headroom of the reference ladder is considered to be a main
bottleneck in the implementation of flash ADCs in deep-submicron
technologies with reduced supply voltage, extending the reference
voltage beyond the input voltage range is highly undesirable.
The principal objective of this thesis is to develop a new circuit
technique to enhance the bandwidth-accuracy product of flash ADCs.
Thus, first, a rigorous analysis of flash ADC architectures accuracy-bandwidth tradeoff is presented.
It is demonstrated that the interpolating architecture achieves a superior accuracy compared
to that of a full flash architecture for the same input capacitance, and hence would lead to
a higher bandwidth-accuracy product, especially in deep-submicron technologies that use low power supplies. Also, the
gain obtained, when interpolation is employed, is quantified. In addition, the limitations of a previous
claim, which suggests that an interpolating architecture is equivalent to an averaging
full flash architecture that trades off accuracy for the input capacitance, is presented. Secondly, a termination
technique for the averaging/interpolation network of flash ADC preamplifiers is devised. The proposed technique maintains the linearity of the ADC at the transfer
characteristics edges and cancels out the over-range voltage, consumed by the dummy preamplifiers. This makes flash ADCs more amenable for integration in deep-submicron CMOS technologies. In addition, the
elimination of this over-range voltage allows a larger
least-significant bit. As a result, a higher input referred offset
is tolerated, and a significant reductions in the ADC input
power dissipation are achieved at the same accuracy. Unlike a previous solution, the proposed
technique does not introduce negative transconductance at flash ADC preamplifiers array edges.
As a result, the offset averaging technique can be used efficiently.
To prove the resulting saving in the ADC input capacitance and power
dissipation that is attained by the proposed termination technique,
a 6-bit 1.6-GS/s flash ADC test chip is designed and implemented in
0.13-$\mu$m CMOS technology. The ADC consumes 180 mW from a 1.5-V
supply and achieves a Signal-to-Noise-plus-Distortion Ratio (SNDR)
of 34.5 dB and 30 dB at 50-MHz and 1450-MHz input signal frequency,
respectively. The measured peak Integral-Non-Linearity (INL) and
Differential-Non-Linearity (DNL) are 0.42 LSB and 0.49 LSB,