Process spaces and formal verification of asynchronous circuits

dc.contributor.author	Negulescu, Radu.	en
dc.date.accessioned	2006-07-28 19:27:00 (GMT)
dc.date.available	2006-07-28 19:27:00 (GMT)
dc.date.issued	1998	en
dc.date.submitted	1998	en
dc.identifier.uri	http://hdl.handle.net/10012/329
dc.format	application/pdf	en
dc.format.extent	8270434 bytes
dc.format.mimetype	application/pdf
dc.language.iso	en	en
dc.publisher	University of Waterloo	en
dc.rights	Copyright: 1998, Negulescu, Radu.. All rights reserved.	en
dc.subject	Harvested from Collections Canada	en
dc.title	Process spaces and formal verification of asynchronous circuits	en
dc.type	Doctoral Thesis	en
dc.pending	false	en
uws-etd.degree	Ph.D.	en
uws.typeOfResource	Text	en
uws.peerReviewStatus	Unreviewed	en
uws.scholarLevel	Graduate	en