| dc.description.abstract | To cope with the ever-increasing demand for higher data rates, reduced latency, and improved coverage, new technologies are needed to advance the current state of wireless communication systems. One of the promising new additions to fifth-generation (5G) basestations is the use of massive multiple-input multiple-output (MIMO) technology. The key concept is to equip the basestation with tens or hundreds of radio-frequency (RF) transceiver chains, all utilizing the same time-frequency resources simultaneously. The additional degrees of freedom this offers allows the basestation to serve multiple users in the same resource block and enables multi-fold improvements in spectral efficiency. Nevertheless, this increase in the number of chains, coupled with the expected increase in transmission bandwidths, complicates the hardware design process and magnifies the impact of hardware imperfections on the system performance.
Mitigating hardware limitations and imperfections in conventional single-input single-output (SISO) transmitters is a well-established discipline, and extending most of the techniques developed for SISO transmitters to the MIMO case is relatively straightforward. The most prominent exception to this, however, is digital predistortion (DPD), which has been the most popular power amplifier (PA) linearization technique for the past three decades. The successful application of DPD to massive MIMO transmitters faces two major challenges. First, reducing the size and cost of the basestation necessitates placing the transmitter antennas in close proximity, which leads to unavoidable inter-antenna coupling. The combination of the PAs' nonlinearity and inter-antenna coupling gives rise to nonlinear crosstalk effects that cannot be mitigated using conventional DPD techniques. This phenomenon is exacerbated by the need to track the dynamic multi-user channel and update the employed precoding accordingly, the result of which is the constant variation in the average-power levels transmitted by the different PAs. Second, since tens or hundreds of low-power PAs are to be employed instead of a single high-power one, the overhead power budget for per-chain DPD must be reduced to maintain a reasonable overall efficiency. The power overhead incurred includes the power consumed by the real-time DPD engine, as well as that consumed by the transmitter-observation receiver (TOR) needed to train the DPD module.
The main objective of this work is developing robust and effective digital signal processing (DSP) techniques that mitigate the combined effects of PA nonlinearity and antenna crosstalk in massive MIMO transmitters. The thesis starts by investigating the impact of precoding on the average-power levels transmitted by the different RF chains, and analyzing the effect this has on the active impedances seen by the PAs in the presence of antenna crosstalk. It is shown that, although precoding is a system-level function that mitigates multi-user channel effects, it has a direct impact on the RF performance of the PAs. Hence, the DPD and precoding subsystems cannot be operated independently from one another. Based on this analysis, we propose two solutions to the problem. The first comprises a load-dependent DPD architecture and a low-complexity algorithm that reduces the disparity in average-power levels arising from conventional precoding schemes. The second solution comprises alternate precoding schemes that fully eliminate the disparity in average-power levels across the RF chains and, consequently, simplify the required DPD architecture. Both solutions ensure a stable performance across all channel conditions.
The second objective of this work is reducing the computational and power overheads of the DPD subsystem. To this end, we propose a computationally efficient algorithm for estimating the delay and phase offsets between the transmitter and the TOR used for DPD training. The proposed algorithm is less resource-consuming and more accurate than the exhaustive search methods employed in the literature. In addition, we propose a low-complexity real-time DPD architecture that requires less hardware resources to implement, introduces less latency, and consumes less power when compared with prior works. | en |
