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dc.contributor.authorCurrie, Alex
dc.date.accessioned2022-01-21 13:46:10 (GMT)
dc.date.available2022-01-21 13:46:10 (GMT)
dc.description.abstractSilicon quantum dots present themselves as a promising implementation for quantum information processing due to the fact that they possess a small chip foot-print, yield high coherence times and are able to leverage the semiconductor industry. These nanoscopic devices rely on forming an electrostatic confinement for individual electrons. To accomplish this, an overlapping metallic gate geometry is implemented. The overlapping metallic gates are typically electrically isolated from one another by an insulating asher oxide layer. Due to unreliable processes during quantum dot fabrication, we substitute the asher oxide for a more robust and reliable oxide. For this, gate-oxide test structures are fabricated to simulate the overlapping gate geometry while various oxides are grown and deposited. It is found that oxides, grown by either ashing or hotplate in tandem with atomic layer deposited Al2O3, yield substantially higher breakdown voltages than conventional methods. One issue single electron spin qubits face is noise generated by charge traps. Charge traps appear at the Si/Oxide interface and seriously impedes many aspects of a quantum processor such as qubit coherence times, electrostatic screening effects and two-qubit gate fidelities. Here, we characterize the density of interface traps on a multitude of oxides found in the Quantum Nano-Fabrication and Characterization Facility. These oxides in clude plasma enhanced chemical vapour deposition (PECVD) SiO2, Tystar dry oxidation, commercial thermal SiO2, atomic layer deposition (ALD) Al2O3 and ALD HfO2. We find that each of these oxides is plagued by a high density of fixed charge and interface traps. We also implement forming gas anneals at high temperature to help passivate the charge traps. It is found that a forming gas anneal at 400C for 10 minutes reduces the number of interface traps by several orders of magnitude and that PECVD SiO2 and ALD Al2O3 host the smallest interface trap density of approximately 1010 eV−1 cm−2 . A major issue facing this implementation of quantum computing is the ability to scale up. Current methods of single qubit rotation are electron spin resonance and electron dipole spin resonance. In either method, a high frequency (HF) transmission line is placed nearby the quantum dots. For a large scale quantum computer, hundreds to thousands of transmission lines and therefore HF interconnects will be necessary, dramatically increasing the complexity of the device and reducing the qubit packing density. In this thesis, we present an elegant solution, dramatically reducing the need for many interconnects. A superconducting microresonator sits directly above the quantum processor providing an oscillatory magnetic field to perform single qubit rotations over an area of 1 mm2 . With a modest quantum dot pitch of 100 nm, approximately 40 million qubits can fit within this region. The resonator possess a unique shape to minimize the electric field component while maximizing the magnetic field ‘felt’ by the qubits. Electrons are tuned on and off of iv resonance by electrostatic tuning of the electron g-factor. We fabricate and characterize a prototype resonator’s transmission coefficient to determine its resonant frequency at room temperature and at 1.4K. Both measurements agree with simulations with a resonance frequency of approximately 16 GHz.en
dc.publisherUniversity of Waterlooen
dc.subjectquantum dotsen
dc.subjectspin qubitsen
dc.subjectquantum computingen
dc.titleCharacterization of gate oxides and microwave resonators for silicon spin qubit devicesen
dc.typeMaster Thesisen
uws-etd.degree.departmentPhysics and Astronomyen
uws-etd.degree.disciplinePhysics (Quantum Information)en
uws-etd.degree.grantorUniversity of Waterlooen
uws-etd.degreeMaster of Scienceen
uws.contributor.advisorBaugh, Jonathan
uws.contributor.affiliation1Faculty of Scienceen

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