Improving the Performance of Nanoscale Field-Effect Transistors Through Electrostatic Engineering

Abstract

The continued scaling of field-effect transistors (FETs) requires that nearly every aspect of these devices be optimized to ensure that they can continue to meet practical performance requirements. However, scaling the channel lengths of FETs naturally enhances electrostatic and quantum mechanical short-channel effects, thereby increasing leakage currents in the OFF-state, reducing driving currents in the ON-state, and making it difficult for FETs attain optimal switching behaviours. To mitigate these detrimental effects, it is imperative to (i) thoroughly understand the electrostatic operation of nanoscale FETs and (ii) establish novel design strategies to mitigate short-channel effects.

In this thesis, I address these two challenges by studying the electrostatic operation of nanoscale FETs using simulation techniques. In particular, I use the non-equilibrium Green's function method, an atomistic quantum transport simulation technique, to study the electrostatic operation of MOSFETs and to assess the utility of novel electrostatic design strategies for nanoscale FETs.

The body of this thesis is divided into three main works. In the first, I study how individual elements of a metal-oxide-semiconductor FET's (MOSFET's) semiconductor's anisotropic permittivity affect device performance, and I establish electrostatic-based guidelines for selecting optimal semiconductors for future MOSFETs. Next, I study how replacing an FET's conventional isotropic insulators (i.e. gate insulator and spacers) with anisotropic insulators can improve the performance of both conventional MOSFETs and tunnel FETs, and I propose novel insulator architectures to further optimize the performance of these devices. Finally, in my third study, I examine how fringe-induced barrier lowering, an electrostatic short-channel effect created by implementing high-κ gate insulators, can be exploited to suppress quantum mechanical short-channel effects (source-to-drain tunneling) to improve the overall performance of nanoscale MOSFETs. The operating principles and design rules established in these three works extend the current picture of the electrostatic operation and design rules for nanoscale FETs to help device designers continue to scale FETs while meeting essential performance benchmarks.