VLSI low-power digital signal processing

Abstract

This thesis reports on new high-level low-power design techniques for digital signal processing for wireless portable systems. Through proper choice and optimization of an algorithm or an architecture, significant power dissipation saving is achieved. Up to an order of magnitude, with little or no degradation in speed or SNR performance, is achieved.

At the heart of these techniques is the minimization of the computational complexity, by the elimination of redundant and irrelevant computations. Redundant computations are extra computations that can be eliminated by applying appropriate transformations to an architecture or an algorithm without changing its functionality. Irrelevant computations are necessary computations that can be eliminated by optimizing the datapath width.

The elimination of redundant computations has been applied to the design of a division algorithm. The division algorithm generates the quotient in the minimum signed-digit representation. Hence, the number of addition/subtraction operations is minimized.

A subband coding image compression algorithm with a simplified filtering structure that requires only addition and subtraction operations has been developed. This simplified filtering structure reduces the power dissipation by 23 times. A new vector quantization algorithm, having a simplified decoding structure, has also been developed for this subband coding algorithm.

The increased flexibility and functionality of signal processing in the digital domain is pushing digital signal processing more and more into the arena of high-speed analog signals. To be able to do this high-speed high-resolution analog-to-digital converters are required. Sigma-Delta A/D converters have been known for their high resolution capabilities using low-precision components.

Parallelism by 4x of analog signal processors is applied to the design of a bandpass Sigma-Delta modulator. The speed of the modulator is increased without increasing the speed requirement of the individual building blocks.

The elimination of redundant and irrelevant computations has been employed in the design of the decimation filter. The decimation filter consists of two parts, the Sinc decimator and a lowpass decimation filter. In the Sinc decimator, the computational redundancy is minimized. The datapath width of the Sinc decimator is optimized to eliminate irrelevant computations.

The lowpass decimation filter employs multiplication minimization, and operation interleaving to reduce the power dissipation. Furthermore, the lowpass decimation filter is designed to be resolution-programmable, allowing the deactivation of the blocks corresponding to the least significant bits when a lower resolution is sufficient. The decimation filter has been designed in a 0.5um, 3.3 Volt CMOS technology.

Eliminating the pre-filter multiplier substantially reduces the power dissipation of a digital channel selection algorithm. The pre-filter multiplier has been substituted by less computationally complex operators, such as multiplexers and XOR gates. The frequency spectrum is divided into four frequency bands. This reduces the filter sharpness requirements, and hence contributes to the power saving. This algorithm achieves up to an order of magnitude saving in power dissipation.