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dc.contributor.authorLi, Chunxiao
dc.date.accessioned2019-09-09 12:48:50 (GMT)
dc.date.available2019-09-09 12:48:50 (GMT)
dc.date.issued2019-09-09
dc.date.submitted2019-09-02
dc.identifier.urihttp://hdl.handle.net/10012/15024
dc.description.abstractRestart policy is a widely used class of techniques integral to the efficiency of conflict-driven clause-learning (CDCL) SAT solvers. While the utility of such policies has been well-established, to-date we still lack a deep theoretical understanding of why restart policies are crucial to the power of CDCL SAT solvers. In this paper, we provide a series of results that theoretically establish the power of restarts for various models of Boolean SAT solvers. More precisely, we make the following contributions. First, we show that certain model of CDCL solvers with restarts are no more powerful from a proof-complexity theoretic point of view than the same configurations without restarts. Second, we define \textit{decision depth} for DPLL proofs of an unsatisfiable formula $\varphi$, and then we relate decision depth of $\varphi$ and size of DPLL proofs (or the running time of a DPLL based solver) for $\varphi$. Third, we introduce a new class of satisfiable instances called $Ladder_n$, then we use decision depth as a tool to proved that a drunk style DPLL solver with restarts can solve $Ladder_n$ in polynomial time with high probability while the solvers with the same configuration without restarts have exponential run time with high probability. Finally, the crucial insight that drives this line of research is the fact that restarts add proof-theoretic or algorithmic power to solver configurations by compensating for the weaknesses of some other important heuristics like branching or value selection or clause learning.en
dc.language.isoenen
dc.publisherUniversity of Waterlooen
dc.subjectproof complexityen
dc.subjectpower of restartsen
dc.subjectbranching heuristicsen
dc.titleTowards a Theoretical Understanding of the Power of Restart in SAT solversen
dc.typeMaster Thesisen
dc.pendingfalse
uws-etd.degree.departmentElectrical and Computer Engineeringen
uws-etd.degree.disciplineElectrical and Computer Engineeringen
uws-etd.degree.grantorUniversity of Waterlooen
uws-etd.degreeMaster of Applied Scienceen
uws.contributor.advisorGanesh, Vijay
uws.contributor.affiliation1Faculty of Engineeringen
uws.published.cityWaterlooen
uws.published.countryCanadaen
uws.published.provinceOntarioen
uws.typeOfResourceTexten
uws.peerReviewStatusUnrevieweden
uws.scholarLevelGraduateen


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