A Novel Retro-directive Phased Array Antenna Architecture

Abstract

Mobile wireless communication scenarios can range from a simple indoor WiFi link to a satellite internet connection to an airplane. Virtually in all scenarios, dynamic changes in the propagation environment or the movement of transmitter and receiver are inevitable. Therefore, the wireless link often experiences quality degradation or even interruption. Adaptive antenna arrays offer a promising solution to combat wireless channel impairments as they adaptively reshape their radiation pattern. For two-way communication, an antenna should be retro-directive meaning its transmit and receive beams are aligned. To achieve retro-directivity, techniques based on direction-of-arrival and self-phasing can be used. The former usually calls for a complex calibration routine to estimate the direction of arrival and beamsteering; the latter relies on the received signal to generate the transmit beam, imposing several limitations on its adaptability. In this thesis, a novel retro-directive phased array architecture is proposed that does not require calibration and which generates its transmit wave independently of its receive wave. Moreover, its radiation pattern can be adaptively shaped by a simple beamforming algorithm, while its transmitted and received beams remain aligned. Structurally, it is comprised of independent modules that can be placed in virtually any arrangement without any hardware modification. The architecture uses the LO phase-shifting technique to steer its beams. The LO signals are generated with a novel frequency synthesizer; it creates a pair of LO signals for the transmission and reception paths to achieve retro-directivity. The proposed antenna architecture is demonstrated practically using a 10-element prototype, verifying its ability to steer the transmit and receive beams while keeping them aligned. In addition, two of the key circuit components of the LO synthesizer, a fractional frequency divider and a novel phase-conjugating phase shifter, are designed and successfully implemented on 65nm CMOS technology, paving the path for use in future applications.