Semiconductor Device Characterization and Modelling for Effective Design of 5G Front-Ends
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Date
2018-11-27
Authors
Raslan, Ahmed
Journal Title
Journal ISSN
Volume Title
Publisher
University of Waterloo
Abstract
The realization of fifth-generation mobile communication will require transceiver front-ends that can handle data-rates of multi-gigabits per second. To provide such data-rates, bandwidth in the hundreds of megahertz will need to be available; hence, moving to millimeter wave frequencies is a must. Utilizing millimeter waves will provide a very high level of integration to the transceiver system, and concepts such as massive multiple-input-multiple-output could be exploited to enable higher data capacities. In order to design such a front-end, accurate simulation tools for both the system and circuit levels are needed. The first is needed because a high-level of integration prevents any opportunity for post-fabrication tweaking; accurate simulation will optimize a first-pass design. The second is essential to preserve the overall efficiency of the system; configurations incorporating a large number of power amplifiers (PAs) will require new design methodologies to enable linear and efficient operation. Unfortunately, existing transistor models cannot be used for these simulations as they cannot predict the device behaviour under real-life operating conditions (i.e., under modulated signal stimulus).
The objective of this thesis is to propose a transistor model that can be used in circuit simulators under any stimulus, including modulated signals. This means that the proposed model will need to be accurate both globally and locally. While the former property relates to the compact modelling approach, the latter relates to behavioural modelling. Thus, the proposed model will bridge the gap between the two modelling approaches.
This thesis starts by studying existing compact and behavioural modelling techniques for radio frequency power transistors. These techniques will be grouped based on the common properties imposed by the model structure (i.e., model formulation and extraction measurements) to help with problem identification. Based on this study, high-order network parameters (HONPs) are proposed. HONPs represent a new set of Volterra-based network parameters that are capable of completely describing weakly-nonlinear (WNL) behaviours of the transistor, and hence guaranteeing the local accuracy of the model. It will be proven, in both measurement and simulation environments, that these parameters exhibit the same properties of linear network parameters represented in power independency, and solution continuity and uniqueness. Therefore, HONPs represent a true extension of linear network parameters. Furthermore, HONPs will be extracted using continuous-wave (CW) nonlinear vector network analyzer (NVNA) measurements, and their ability to predict the device WNL behaviours will be demonstrated using wideband multi-tone stimuli in both simulation and measurement environments.
Next, a novel compact model that utilizes these parameters as a building block will be proposed. New model formulations and extraction techniques will be presented. Model implementation will be performed in two parts. First, a small-signal model will be generated using a new layered-neural network (NN) technique that allows testing different topologies for the extrinsic and intrinsic shells, in an automated manner. Second, an intrinsic HONPs-based large-signal model will be constructed using a novel NN technique that allows optimizing a nonlinear function to fit first and high-order derivatives simultaneously.
Finally, the proposed model will be tested under different circuit simulators (direct-current, small-signal, harmonic balance and envelope simulators). Modulated signal validations will be shown in the simulation environment. Also, a two-tone measurement validation using a class-AB PA will be presented.
Description
Keywords
Nonlinear Measurements, Nonlinear Circuit Analysis, Transistor Compact Models, Behavioral Models, Linearization