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dc.contributor.authorEmtenan, Ariq 13:27:17 (GMT) 13:27:17 (GMT)
dc.description.abstractDigital integrated circuits (ICs) are the driving force behind computing, communication and entertainment in today’s world. More powerful and energy efficient ICs continue to be designed and built by the semiconductor industry to meet current demands. In addition, complexity in Electronic Design Automation(EDA) software continues to grow to keep up with the design and technological advances in ICs. Design parameters that control various aspects of EDA software, such as synthesis, placement and routing settings, can affect the performance of ICs, and current standard cell logic synthesis and physical design flow tools consist of hundreds of such parameters to be specified by the designer. Discovering the optimal value for each parameter can result in significant performance and power efficiency gains. In this thesis, we develop a proof of concept web tool that uses open source EDA software to generate datasets for a large number of circuits and uses the data to build predictive models using statistical learning techniques. We use these models to select design parameters for the VLSI physical design flow floorplanning and placement stages that minimize the total wirelength of the integrated circuit. Using empirical evaluation on three real-world test circuits, we show a 15x-35x reduction in time spent to discover predicted values of one of the studied parameters that reduces total wire-length with statistical significance compared to a brute force exploration of the design space, with an error rate below 5%. The key contributions of this thesis are: • Development of a web based tool to perform VLSI physical design flow of a standard cell based integrated circuit, as well as to generate and record datapoints at various stages of the flow. • Development and investigation of predictive models through the web based tool, using the recorded datapoints and utilizing statistical learning techniques, to predict VLSI physical design flow floorplanning and placement tool parameters that minimize total wirelength in a particular integrated circuit.en
dc.publisherUniversity of Waterlooen
dc.subjectDigital integrated circuitsen
dc.subjectphysical designen
dc.subjectstatistical learningen
dc.titleMachineFlow: A Web Tool to Adaptively Select EDA Tool Parameters for Digital ICs Using Statistical Learningen
dc.typeMaster Thesisen
dc.pendingfalse and Computer Engineeringen and Computer Engineeringen of Waterlooen
uws-etd.degreeMaster of Applied Scienceen
uws.contributor.advisorGarg, Siddharth
uws.contributor.advisorPatel, Hiren
uws.contributor.affiliation1Faculty of Engineeringen

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