Wright, Derek2006-08-222006-08-2220052005http://hdl.handle.net/10012/809Content addressable memories (CAMs) are gaining popularity with computer networks. Testing costs of CAMs are extremely high owing to their unique configuration. In this thesis, a fault analysis is carried out on an industrial ternary CAM (TCAM) design, and search path test algorithms are designed. The proposed algorithms are able to test the TCAM array, multiple-match resolver (MMR), and match address encoder (MAE). The tests represent a 6x decrease in test complexity compared to existing algorithms, while dramatically improving fault coverage.application/pdf367597 bytesapplication/pdfenCopyright: 2005, Wright, Derek. All rights reserved.Electrical & Computer Engineeringcontent addressable memorydesign for testsemiconductor memorytest algorithmsMaster Thesis