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Worst Case Latency Analysis for Hoplite FPGA-based NoC
Overlay NoCs, such as Hoplite, are cheap to implement on an FPGA but provide no bounds on worst-case routing latency of packets traversing the NoC due to deflection routing. In this paper, we show how to adapt Hoplite to ...
A Dynamic Scratchpad Memory Unit for Predictable Real-Time Embedded Systems
(University of Waterloo, 2013-01-17)
Scratch-pad memory is a popular alternative to caches in real-time embedded systems due to its advantages in terms of timing predictability and power consumption. However, dynamic management of scratch-pad content is ...