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Worst Case Latency Analysis for Hoplite FPGA-based NoC
Overlay NoCs, such as Hoplite, are cheap to implement on an FPGA but provide no bounds on worst-case routing latency of packets traversing the NoC due to deflection routing. In this paper, we show how to adapt Hoplite to ...
A Composable Worst Case Latency Analysis for Multi-Rank DRAM Devices under Open Row Policy
As multi-core systems are becoming more popular in real-time embedded systems, strict timing requirements for accessing shared resources must be met. In particular, a detailed latency analysis for Double Data Rate Dynamic ...
Data Scratchpad Prefetching for Real-time Systems
In recent years, the real-time community has produced a variety of approaches targeted at managing on- chip memory (scratchpads and caches) in a predictable way. However, to obtain safe Worst-Case Execution Time (WCET) ...