Browsing Electrical and Computer Engineering by Type "Technical Report"
Now showing items 1-7 of 7
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APPENDIX to DRAMbulism: Balancing Performance and Predictability through Dynamic Pipelining
(2020-03-02)Worst-case execution bounds for real-time programs are highly impacted by the latency of accessing hardware shared resources, such as off-chip DRAM. While many different memory controller designs have been proposed in the ... -
Appendix to: Dynamic Memory Bandwidth Allocation For Real-Time GPU-Based SOC Platforms
(2020)Appendix to: Dynamic Memory Bandwidth Allocation For Real-Time GPU-Based SOC Platforms -
Astra Version 1.0: Evaluating Translations from Alloy to SMT-LIB
(2019-06-13)We present a variety of translation options for converting Alloy to SMT-LIB via Alloy’s Kodkod interface. Our translations, which are implemented in a library that we call Astra, are based on converting the set and relational ... -
Data Scratchpad Prefetching for Real-time Systems
(2017-05-01)In recent years, the real-time community has produced a variety of approaches targeted at managing on- chip memory (scratchpads and caches) in a predictable way. However, to obtain safe Worst-Case Execution Time (WCET) ... -
Energy Consumption Analysis of XRP Validator
(2020)The XRP Ledger is an open-source payment system with a primary focus on providing an efficient cross-border payment network. The network achieves distributed consensus and prevents double-spending all while remaining ... -
HopliteRT Source Queuing Bound Correction
(2020)We present a correction to the analytical source queuing bound for HopliteRT [1], [2], which addresses the counter-example put forward in Section IV-D of [3] by taking the effect of the in-flight jitter suffered by data ... -
Worst Case Latency Analysis for Hoplite FPGA-based NoC
(2017-10-30)Overlay NoCs, such as Hoplite, are cheap to implement on an FPGA but provide no bounds on worst-case routing latency of packets traversing the NoC due to deflection routing. In this paper, we show how to adapt Hoplite to ...