Browsing Theses by Supervisor "Patel, Hiren"
Now showing items 1-11 of 11
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A Fault Tolerant Core for Parallel Execution of Ultra Reduced Instruction Set (URISC) and MIPS Instructions
(University of Waterloo, 2016-12-13)Modern safety critical systems require the ability to detect and handle situations where an error has occurred. Efficient coding and protection schemes are widely used to protect the communication links and memories of ... -
GPU Wavefront Splitting for Safety-Critical Systems
(University of Waterloo, 2022-10-07)Graphics processing units (GPUs) are compute platforms that are ideal for highly parallel workloads due to their high degree of hardware parallelism. Parallelism offered by GPUs lends itself well to machine learning and ... -
Gromit An In-Memory Graph Database
(University of Waterloo, 2017-02-28)This work presents the implementation of an in-memory graph database management system called Gromit. This graph database represents large and complex networks using labelled property graphs, and encodes semantic information ... -
An Implementation of a Predictable Cache-coherent Multi-core System
(University of Waterloo, 2019-05-21)Multi-core platforms have entered the realm of the embedded systems to meet the ever growing performance requirements of the real-time embedded applications. Real-time applications leverage the hardware parallelism from ... -
MachineFlow: A Web Tool to Adaptively Select EDA Tool Parameters for Digital ICs Using Statistical Learning
(University of Waterloo, 2016-10-26)Digital integrated circuits (ICs) are the driving force behind computing, communication and entertainment in today’s world. More powerful and energy efficient ICs continue to be designed and built by the semiconductor ... -
Managing HBM’s bandwidth in Multi-Die FPGAs using Overlay NoCs
(University of Waterloo, 2022-01-18)We can improve HBM bandwidth distribution and utilization on a multi-die FPGA like Xilinx Alveo U280 by using Overlay Network-on-Chips (NoCs). HBM in Xilinx Alveo U280 offers 8GBs of memory capacity with a theoretical ... -
PASoC: A Predictable Accelerator Rich SoC for Safety-Critical Systems
(University of Waterloo, 2023-09-21)This thesis presents a model of a Predictable Accelerator-rich System-on-Chip (PASoC) for safety-critical systems, which guarantees timing predictability of a memory access in the system. Earlier adoption of accelerator-rich ... -
Predictable Cache Coherence Protocols for Mixed-Time-Criticality Multi-core Systems
(University of Waterloo, 2017-09-18)Modern real-time systems consist of a combination of hard real-time, firm real-time and soft real-time tasks. Hard real-time (HRT) tasks mandate strict timing requirements by requiring that a static timing analysis can be ... -
Predictable Shared Memory Resources for Multi-Core Real-Time Systems
(University of Waterloo, 2017-04-18)A major challenge in multi-core real-time systems is the interference problem on the shared hardware components amongst cores. Examples of these shared components include buses, on-chip caches, and off-chip dynamic random ... -
Strengthening Physical Unclonable Functions using Composition
(University of Waterloo, 2019-08-22)We explore the idea of composing PUFs with the intent that the resultant PUF is stronger than the constituent PUFs. Prior work has proposed a construction, which sub- sequent work has shown to be weak. We revisit this prior ... -
Timing Predictable and High-Performance Hardware Cache Coherence Mechanisms for Real-Time Multi-Core Platforms
(University of Waterloo, 2021-06-18)Multi-core platforms are becoming primary compute platforms for real-time systems such as avionics and autonomous vehicles. This adoption is primarily driven by the increasing application demands deployed in real-time ...