Browsing University of Waterloo by Author "Pellizzoni, Rodolfo"
Now showing items 1-9 of 9
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APPENDIX to DRAMbulism: Balancing Performance and Predictability through Dynamic Pipelining
Mirosanlou, Reza; Hassan, Mohamed; Pellizzoni, Rodolfo (2020-03-02)Worst-case execution bounds for real-time programs are highly impacted by the latency of accessing hardware shared resources, such as off-chip DRAM. While many different memory controller designs have been proposed in the ... -
Appendix to: Dynamic Memory Bandwidth Allocation For Real-Time GPU-Based SOC Platforms
Aghilinasab, Homa; Ali, Waqar; Yun, Heechul; Pellizzoni, Rodolfo (2020)Appendix to: Dynamic Memory Bandwidth Allocation For Real-Time GPU-Based SOC Platforms -
A Composable Worst Case Latency Analysis for Multi-Rank DRAM Devices under Open Row Policy
Wu, Zheng Pei; Pellizzoni, Rodolfo; Guo, Danlu (Springer, 2017-04-12)As multi-core systems are becoming more popular in real-time embedded systems, strict timing requirements for accessing shared resources must be met. In particular, a detailed latency analysis for Double Data Rate Dynamic ... -
Data Scratchpad Prefetching for Real-time Systems
Soliman, Muhammad Refaat Sedky; Pellizzoni, Rodolfo (2017-05-01)In recent years, the real-time community has produced a variety of approaches targeted at managing on- chip memory (scratchpads and caches) in a predictable way. However, to obtain safe Worst-Case Execution Time (WCET) ... -
Duetto: Latency Guarantees at Minimal Performance Cost
Mirosanlou, Reza; Hassan, Mohamed; Pellizzoni, Rodolfo (IEEE Design, Automation and Test in Europe Conference (DATE), 2021-02-05)The management of shared hardware resources in multi-core platforms has been characterized by a fundamental trade-off: high-performance arbiters typically employed in COTS systems offer no worst-case guarantees, while ... -
DuoMC: Tight DRAM Latency Bounds with Shared Banks and Near-COTS Performance
Mirosanlou, Reza; Hassan, Mohamed; Pellizzoni, Rodolfo (ACM International Symposium on Memory Systems (MEMSYS 2021), 2021-09-27)DRAM memory controllers (MCs) in COTS systems are designed primarily for average performance, offering no worst-case guarantees, while real-time MCs provide timing guarantees at the cost of a significant average performance ... -
HopliteRT Source Queuing Bound Correction
Elmor Lang, Ian; Pellizzoni, Rodolfo; Kapre, Nachiket (2020)We present a correction to the analytical source queuing bound for HopliteRT [1], [2], which addresses the counter-example put forward in Section IV-D of [3] by taking the effect of the in-flight jitter suffered by data ... -
A Survey on Cache Management Mechanisms for Real-Time Embedded Systems
GRACIOLI, GIOVANI; ALHAMMAD, AHMED; MANCUSO, RENATO; FRÖHLICH, ANTÔNIO; Pellizzoni, Rodolfo (Association of Computing Machinery, 2015-11)Multicore processors are being extensively used by real-time systems, mainly because of their demand for increased computing power. However, multicore processors have shared resources that affect the predictability of ... -
Worst Case Latency Analysis for Hoplite FPGA-based NoC
Wasly, Saud; Pellizzoni, Rodolfo; Kapre, Nachiket (2017-10-30)Overlay NoCs, such as Hoplite, are cheap to implement on an FPGA but provide no bounds on worst-case routing latency of packets traversing the NoC due to deflection routing. In this paper, we show how to adapt Hoplite to ...