Now showing items 1-2 of 2

    • HopliteRT Source Queuing Bound Correction 

      Elmor Lang, Ian; Pellizzoni, Rodolfo; Kapre, Nachiket (2020)
      We present a correction to the analytical source queuing bound for HopliteRT [1], [2], which addresses the counter-example put forward in Section IV-D of [3] by taking the effect of the in-flight jitter suffered by data ...
    • Worst-Case Latency Analysis for the Versal Network-on-Chip 

      Elmor Lang, Ian (University of Waterloo, 2022-01-18)
      The recent line of Versal FPGA devices from Xilinx Inc. includes a hard Network-On-Chip (NoC) embedded in the programmable logic, designed to be a high-performance system-level interconnect. While the target markets for ...

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