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http://hdl.handle.net/10012/764
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| Title: | Cache Coherency for Symmetric Multiprocessor Systems on Programmable Chips |
| Authors: | Hung, Austin |
| Keywords: | Electrical & Computer Engineering
FPGA
SOPC
SMP
cache coherency |
| Approved Date: | 2004 |
| Date Submitted: | 2004 |
| Abstract: | Rapid progress in the area of Field-Programmable Gate Arrays (FPGAs) has led to the availability of softcore processors that are simple to use, and can enable the development of a fully working system in minutes. This has lead to the enormous popularity of System-On-Programmable-Chip (SOPC) computing platforms. These softcore processors, while relatively simple compared to their leading-edge hardcore counterparts, are often designed with a number of advanced performance-enhancing features, such as instruction and data caches. Moreover, they are designed to be used in a uniprocessor or uncoupled multiprocessor architecture, and not in a tightly-coupled multiprocessing architecture. As a result, traditional cache-coherency protocols are not suitable for use with such systems. This thesis describes a system for enforcing cache coherency on symmetric multiprocessing (SMP) systems using softcore processors. A hybrid protocol that incorporates hardware and software to enforce cache coherency is presented. |
| Department: | Electrical and Computer Engineering |
| Degree: | Master of Applied Science |
| URI: | http://hdl.handle.net/10012/764 |
| Appears in Collections: | Faculty of Engineering Theses and Dissertations
Electronic Theses and Dissertations (UW)
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