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|Title: ||Hardware Implementation of a High Speed Deblocking Filter for the H.264 Video Codec|
|Authors: ||Dickey, Brian|
|Approved Date: ||25-Apr-2012 |
|Date Submitted: ||2012 |
|Abstract: ||H.264/MPEG-4 part 10 or Advanced Video Coding (AVC) is a standard for video compression. MPEG-4 is currently one of the most widely used formats for recording, compression and distribution of high definition video. One feature of the AVC codec is the inclusion of an in-loop deblocking filter.
The goal of the deblocking filter is to remove blocking artifacts that exist at macroblock
boundaries. However, due to the complexity of the deblocking algorithm, the filter can
easily account for one-third of the computational complexity of a decoder.
In this thesis, a modification to the deblocking algorithm given in the AVC standard
is presented. This modification allows the algorithm to finish the filtering of a macroblock
to finish twenty clock cycles faster than previous single filter designs.
This thesis also presents a hardware architecture of the H.264 deblocking filter to be
used in the H.264 decoder. The developed architecture allows the filtering of videos streams using 4:2:2 chroma subsampling and 10-bit pixel precision in real-time.
The filter was described in VHDL and synthesized for a Spartan-6 FPGA device. Timing analysis showed that is was capable of filtering a macroblock using 4:2:0 chroma subsampling in 124 clock cycles and 4:2:2 chroma subsampling streams in 162 clock cycles. The filter can also provide real-time deblocking of HDTV video (1920x1080) of up to 988 frames per second.|
|Program: ||Electrical and Computer Engineering|
|Department: ||Electrical and Computer Engineering|
|Degree: ||Master of Applied Science|
|Appears in Collections:||Faculty of Engineering Theses and Dissertations |
Electronic Theses and Dissertations (UW)
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