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http://hdl.handle.net/10012/3407
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| Title: | Low Power Clock and Data Recovery Integrated Circuits |
| Authors: | Ardalan, Shahab |
| Keywords: | CDR
Low Power
CMOS
PLL
Clock and Data Recovery
Integrated Circuit |
| Approved Date: | 24-Oct-2007 |
| Date Submitted: | 22-Oct-2007 |
| Abstract: | Advances in technology and the introduction of high speed processors have increased the demand for fast, compact and commercial methods for transferring large amounts of data. The next generation of the communication access network will use optical fiber as a media for data transmission to the subscriber. In optical data or chip-to-chip data communication, the continuous received data needs to be converted to discrete data. For the conversion, a synchronous clock and data are required. A clock and data recovery (CDR) circuit recovers the phase information from the data and generates the in-phase clock and data.
In this dissertation, two clock and data recovery circuits for Giga-bits per second (Gbps) serial data communication are designed and fabricated in 180nm and 90nm CMOS technology. The primary objective was to reduce the circuit power dissipation for multi-channel data communication applications. The power saving is achieved using low swing voltage signaling scheme. Furthermore, a novel low input swing Alexander phase detector is introduced. The proposed phase detector reduces the power consumption at the transmitter and receiver blocks.
The circuit demonstrates a low power dissipation of 340µW/Gbps in 90nm CMOS technology. The CDR is able to recover the input signal swing of 35mVp. The peak-to-peak jitter is 21ps and RMS jitter is 2.5ps. Total core area excluding pads is approximately 0.01mm2. |
| Program: | Electrical and Computer Engineering |
| Department: | Electrical and Computer Engineering |
| Degree: | Doctor of Philosophy |
| URI: | http://hdl.handle.net/10012/3407 |
| Appears in Collections: | Faculty of Engineering Theses and Dissertations
Electronic Theses and Dissertations (UW)
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